八选一数据选择器用VHDL设计方法。

显示全部楼层 · 2010-4-22 15:21:40

library ieee;use ieee.std_logic_1164.all;entity mux8_1 isport(kd:in std_logic_vector(2 downto 0);
input:in std_logic_vector(7 downto 0);
output:out std_logic);end;architecture art of mux8_1 isbeginprocess(kd,input)beginif kd="000" thenoutput<=input(0); elsif kd="001" thenoutput<=input(1);elsif kd="010" thenoutput<=input(2);elsif kd="011" thenoutput<=input(3);elsif kd="100" thenoutput<=input(4);elsif kd="101" thenoutput<=input(5);elsif kd="110" thenoutput<=input(6);elsif kd="111" thenoutput<=input(7);else null;end if;end process;end art;

千问 · 2010-4-22 15:21:40

libraryieee;useieee.std_logic_1164.all;entitymux8_1isport(kd:instd_logic_vector(2downto0);input:instd_logic_vector(7downto0);output:outstd_logic);end;architectureartofmux8_1isbeginprocess(kd,input)beginifkd="000"thenoutput<=input(0);elsifkd="001"thenoutput<=input(1);elsifkd="010"thenoutput<=input(2);elsifkd="011"thenoutput<=input(3);elsifkd="100"thenoutput<=input(4);elsifkd="101"thenoutput<=input(5);elsifkd="110"thenoutput<=input(6);elsifkd="111"thenoutput<=input(7);elsenull;endif;endprocess;endart;