谁来帮帮忙让这些文字翻译成英文！谢谢！急急急！

显示全部楼层 · 2008-5-16 11:48:26

Abstract: The accumulator is the arithmetic operation elemental area, may have many kinds of realizes the structure, uses the resources which and the operation speed the different structure realizes it to consume also respectively has not same. This article studied one with to realize based on the VHDL language accumulator's design, analyzed to the respective performance compares, based on this has designed a 8bit accumulator. And in Xilinx Corporation's ISE under the 5.7e software environment, used VHDL and Verilog the HDL hardware description language carries on the design to realize and to use Modelsim to carry on the simulation confirmation, based on this has carried on the comparative analysis to its performance. 关键词：加法器 FPGA VHDL Modelsim软件

千问 · 2008-5-16 11:48:26

Based on the addition of VHDL design Abstract: Adder is the basic unit of arithmetic operations, can have a variety of structures, the different structure to achieve its consumption of resources and the computing speed have not the same. In this paper, a language based on VHDL addition to the design and implementation of their performance to be analyzed and compared, on the basis of the design of an 8 bit adder. And Xilinx's ISE 5.7e software environment, using VHDL and Verilog HDL hardware description language for the design and realization of a simulation using Modelsim, on the basis of their performance of a comparative analysis. Key words: Adder FPGA VHDL Modelsim software

千问 · 2008-5-16 11:48:26

The accumulator is the arithmetic operation elemental area, may have many kinds of realizes the structure, uses the resources which and the operation speed the different structure realizes it to consume also respectively has not same. This article studied one with to realize based on the VHDL language accumulator's design, analyzed to the respective performance compares, based on this has designed a 8bit accumulator. And in Xilinx Corporation's ISE under the 5.7e software environment, used VHDL and Verilog the HDL hardware description language carries on the design to realize and to use Modelsim to carry on the simulation confirmation, based on this has carried on the comparative analysis to its performance. 加法器 AccumulatorFPGA VHDL Modelsim软件FPGA VHDL Modelsim software

千问 · 2008-5-16 11:48:26

Adder is the basic unit of arithmetic operations, can have a variety of structures, the different structure to achieve its consumption of resources and the computing speed have not the same. In this paper, a language based on VHDL addition to the design and implementation of their performance to be analyzed and compared, on the basis of the design of an 8 bit adder. And Xilinx's ISE 5.7e software environment, using VHDL and Verilog HDL hardware description language for the design and realization of a simulation using Modelsim, on the basis of their performance of a comparative analysis