shared variable没问题 用vhdl描述双端口ram就需要用到比如：architecture syn of rams_16 istype RAMtype is array (0 to 255) of std_logic_vector(15 downto 0);shared variable RAM : RAMtype;begin
process (CLKA)
begin
if CLKA'event and CLKA = '1' then
if ENA = '1' then
if WEA = '1' then
