library ieee;
use ieee.std_logic_1164.all;
entity myand is
port
(
m,q: in std_logic;
aout: out std_logic
);
end myand;
architechture and1 of myand is
begin
aout<= m and q;
end and1;
机器报错 Error (10500): VHDL syntax error at myand.vhd(10) near text "archtechture";expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration".
求各位大侠协助
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