八位乘法器，程序如下：1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ADDER8B is
port (
A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
cin: in std_logic;
s : out std_logic_vector(7 downto 0);
cout: out std_logic);
end ADDER8B;
architecture art of ADDER8B is
signal m:std_logic_vector(8 downto 1);
signal n:std_logic;
begin
process(A,B)
begin
m <= A+B+cin after 2 ns;
n<=m(8);
end process;
s<=m(8 downto 1);
cout<=n;
endart;
2
library ieee;
use ieee.std_logic_1164.all;
entity andarith is
port(abin:in std_logic;
din: in std_logic_vector(7 downto 0);
dout:out std_logic_vector(7 downto 0));
end andarith;
architecture art of andarith is
begin
process(abin,din)
begin
for I in 0 to 7 loop
dout (I)<=din(I)and abin;
end loop;
end process;
end art;
3
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ARICTL is
port (CLK: in std_logic;
START: in std_logic;
CLKOUT:out std_logic;
RSTALL:out std_logic;
ARIEND:out std_logic);
end ARICTL;
architecture art of arictl is
signal CNT4B:std_logic_vector(3 downto 0);
begin
RSTALL<=START;
process(CLK,START)
begin
if START='1' then CNT4B<="0000";
elsif CLK'event and CLK='1' then
if CNT4B<8 then
CNT4B<=CNT4B+1;
end if ;
end if ;
end process;
process(CLK,CNT4B,START)
begin
if START='0' then
if CNT4B<8 then
CLKOUT<=CLK; ARIEND<='0';
else CLKOUT<='0'; ARIEND<='1';
end if;
else
CLKOUT<=CLK;
ARIEND<='0';
end if ;
end process;
end art;
4
library ieee;
use ieee.std_logic_1164.all;
entity REG16B is
port(CLK: in std_logic;
clr:IN STD_LOGIC;
D: in std_logic_VECTOR(8 DOWNTO 0);
Q: out std_logic_vector (15 downto 0));
end REG16B ;
architecture art of REG16Bis
signal r16s: std_logic_vector(15 downto 0);
begin
process(CLK,CLR)
begin
if CLR='1' then r16s<="0000000000000000";
elsif CLK'event and CLK='1'then
r16s(6 downto 0)<=r16s(7 downto 1);
r16s(15 downto 7)<=D;
end if ;
end process;
Q<=r16s;
end art;
5
library ieee;
use ieee.std_logic_1164.all;
entity SREG8B is
port (CLK:in std_logic;
LOAD: in std_logic;
DIN:in std_logic_vector(7 downto 0);
QB: out std_logic);
end SREG8B;
architecture art of SREG8B is
signal REG8:std_logic_vector(7 downto 0);
begin
process(CLK,LOAD)
begin
if CLK'event and CLK='1' then
if LOAD='1' then REG8<=DIN;
else REG8(6 downto 0)<=REG8(7 downto 1);
end if;
end if;
end process;
QB<=REG8(0);
end art;
仿真时波形图有问题：
6为顶层程序，补充在回答里。 我想解决波形图的问题。波形输出不对啊
|
