用vhdl设计四输入与门，两种方法

显示全部楼层 · 2015-6-26 22:32:58

急，谢谢！要过程

千问 · 2015-6-26 22:32:58

第一种方法，程序如下:library ieee；use ieee.std_logic_1164.all；entity and4 is port (a,b,c,d : in std_logic；
z : out std_logic )；end and4；architecture medied of and4 isbegin z <= (a and b) and (c and d)；end medied；第二种方法，程序如下:library ieee；use ieee.std_logic_1164.all；entity and4 is port (a,b,c,d : i

千问 · 2015-6-26 22:32:58

第一种方法，程序如下：library ieee;use ieee.std_logic_1164.all;entity and4 is port (a,b,c,d : in std_logic;
z : out std_logic );end and4;architecture medied of and4 is

千问 · 2015-6-26 22:32:58

一种是根据真值表，用CASE WHEN语句，一种是直接用output<=a and b and c and d;