宏定义了好几次，看不懂。
option.inc
。。。
;(2) Select XTaL
XTAL_SEL SETA 12000000
;XTAL_SEL SETA 16934400
;(3) Select FCLK
FCLKSETA 304000000
;FCLKSETA 296352000
;(4) Select Clock Division (Fclk:Hclk:Pclk)
CLKDIV_VAL EQU 7 ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
[ XTAL_SEL = 12000000
[ FCLK = 271500000
M_MDIVEQU 173;Fin=12.0MHz Fout=271.5MHz
M_PDIVEQU 2
[ CPU_SEL = 32440001
M_SDIVEQU 2; 2440A
|
M_SDIVEQU 1; 2440X
]
]
[ FCLK = 304000000
M_MDIVEQU 68;Fin=12.0MHz Fout=304.8MHz
M_PDIVEQU 1
[ CPU_SEL = 32440001
M_SDIVEQU 1; 2440A
|
M_SDIVEQU 0; 2440X
]
]
[ UCLK = 48000000
U_MDIVEQU 56;Fin=12.0MHz Fout=48MHz
U_PDIVEQU 2
U_SDIVEQU 2
]
[ UCLK = 96000000
U_MDIVEQU 56;Fin=12.0MHz Fout=96MHz
U_PDIVEQU 2
U_SDIVEQU 1
]
| ; else if XTAL_SEL = 16.9344Mhz
[ FCLK = 266716800
M_MDIVEQU 118 ;Fin=16.9344MHz
M_PDIVEQU 2
[ CPU_SEL = 32440001
M_SDIVEQU 2; 2440A
|
M_SDIVEQU 1; 2440X
]
]
[ FCLK = 296352000
M_MDIVEQU 97 ;Fin=16.9344MHz
M_PDIVEQU 1
[ CPU_SEL = 32440001
M_SDIVEQU 2; 2440A
|
M_SDIVEQU 1; 2440X
]
]
[ FCLK = 541900800
M_MDIVEQU 120 ;Fin=16.9344MHz
M_PDIVEQU 2
[ CPU_SEL = 32440001
M_SDIVEQU 1; 2440A
|
M_SDIVEQU 0; 2440X
]
]
[ UCLK = 48000000
U_MDIVEQU 60 ;Fin=16.9344MHz Fout=48MHz
U_PDIVEQU 4
U_SDIVEQU 2
]
[ UCLK = 96000000
U_MDIVEQU 60 ;Fin=16.9344MHz Fout=96MHz
U_PDIVEQU 4
U_SDIVEQU 1
]
] ; end of if XTAL_SEL = 12000000.
。。。
|
