HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register.The storage register has parallel 3-state outputs.Separate clocks are provided for both the shift
register and the storage register.The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered.If the user wishes to connect
both clocks together, the shift register state will always be one clock pulse ahead of the storage register.
Features
*High Speed Operation:tpd (RCK to Q) = 17 ns typ (CL = 50 pF)
*High Output Current:Fanout of 15 LSTTL Loads (QA to QH outputs)
*Wide Operating Voltage:VCC = 2 to 6 V
*Low Input Current:1 μA max
*Low Quiescent Supply Current:ICC (static) = 4 μA max (Ta = 25°C)
Function Table
RCK SCK SCLR G Function
XXXHQto Qhigh impedance
A H
X X L X Shift register cleared Q ’ = L
H
X H X Shift register clocked Q= Q , Q= SER
n n – 1 A
X H X Contents of shift register transferred to output latches
