LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY EAST_BROTHER IS
PORT (CLK50 : IN STD_LOGIC;
KEY1: IN STD_LOGIC;
KEY2: IN STD_LOGIC;
--COUNT :OUT STD_LOGIC_VECTOR(24 DOWNTO 0));-----
Q: OUT STD_LOGIC);
END EAST_BROTHER;
ARCHITECTURE A OF EAST_BROTHER IS
signal S:STD_LOGIC_VECTOR(2 DOWNTO 0):="100";
signal COUNT : STD_LOGIC_VECTOR(24 DOWNTO 0):="0000000000000000000000000";
signal CAO : STD_LOGIC_VECTOR(24 DOWNTO 0);
BEGIN
P_A: PROCESS(KEY1,key2,CLK50,s,count)
--VARIABLE COUNT : STD_LOGIC_VECTOR(24 DOWNTO 0);
--VARIABLE CAO :STD_LOGIC_VECTOR(24 DOWNTO 0);-------
BEGIN
IF KEY1'EVENT AND KEY1='1' THEN S COUNTCOUNTCOUNTCOUNTCOUNT COUNT<="0000000000000000000000000";
END CASE;
IF (CLK50'EVENT AND CLK50='1') THEN
IF CAO=COUNT THEN Q<='1';CAO<="0000000000000000000000000";
ELSE CAO <= CAO+1; Q<='0';
END IF;
END IF;
END PROCESS P_A;
--P_B: PROCESS(CLK50)
--VARIABLE CAO :STD_LOGIC_VECTOR(24 DOWNTO 0);
--BEGIN
-- IF (CLK50'EVENT AND CLK50='1') THEN
--
IF CAO=COUNT THEN Q<='1';CAO:="0000000000000000000000000";
--
ELSE CAO := CAO+1; Q<='0';
--
END IF;
-- END IF;
--END PROCESS P_B;
END A;一上为程序，我想实现可控分频，但是rtl上显示就是key1没接上。
前面有“----”的是调试时设置为无效的，所以不需要看那些。
