Senior Verification Engineer
Job Responsibilities:
Candidate will be responsible for the verification of SoC designs and multi-media algorithm at system and unit levels,developing verification plan to verify design functionality.Furthermore, candidate will code test benches using Verilog and SystemC,
write tools using Perl and shell scripts, utilize advanced verification tools encompassing formal verification, emulation, code coverage. Additionally, candidate will generate tests and debug the Verilog design.
Job Requirement
- At least 3 years direct experience in verifying complex multi-media SoC chips.
- Must be knowledgeable in several of below fields
- Scripting language, Perl/Shell/sed/awk.
- GNU tools, gcc/g++/make/config
- Generated constrained random test using SCV.
- PSL/Sugar assertion language
- The ideal candidate should also be familiar with all stages of ASIC development.
- Position requires strong analytical skills
- Design modeling using SystemC and TLM is a big plus.
- Must be highly motivated and skillful in resolving difficult technical problems
- Good written and spoken English
- Good communication skills and able to work both independently and in a team.
如有意向请将你的中英文简历(word版本)发送至:
[email protected]
注意:请务必注明应聘的职位名称.谢谢. |
