<pre class=\"replyask-text\" id=\"content-2023974\">signal a : sfixed(3 downto -6);
...
s = resize(a*a,7, -6);-- resize using left and right bounds
s = resize(a*a, s);
-- resize using bounds of s
<p class=\"replyask-ref reference gray\"><span class=\"refer-title\">参考资料：</span>The Designer\'s Guide to VHDL - Peter J. Ashenden</p>
