LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4IS
PORT(i0,i1,i2,i3,a,b:INSTD_LOGIC;
q:OUTSTD_LOGIC);
ENDmux4;
ARCHITECTUREbody_mux4OFmux4IS
signalmuxval:integerrange7downto0;
BEGIN
process(i0,i1,i2,i3,a,b)
begin
muxval=0;
if(a=\'1\')thenmuxval=muxval1;endif;
if(b=\'1\')thenmuxval=muxval2;endif;
casemuxvalis
when0=q=i0;
when1=q=i1;
when2=q=i2;
when3=q=i3;
whenothers=null;
endcase;
endprocess;
ENDbody_mux4; |
