The RlSC philosophy seeks an overall reduction in CPU complexity,using a reduction instruction set made up of simple‘building-block’ instructions.These instructions are hardwired into the CPU circuitry, and can then be used to build more complicated instructions.By using thesesimplified instructions,RlSC architecture is able to increase the speed,efficiency and performance of a device by reducing the average number ofcycles necessary to execute an instruction as well as the time per cycle. The strategy behind RlSC is to attain single- cycle operation for all,or most,CPU instructions.This,and other advances in chip technology, will
have profound and far-reaching effects on the logic-analysis instrument market.
Clearly,such dramatic increases in processor performance,together withthe advances made in high-speed memory devices needed to keep pace withRlSC processors,must be matched by ever-increasing acquisition speed of the instruments analysing the device.This will guarantee the furtherdevelopment of the logic analyser over the next few years.
Finally,as circuit and IC design techniques lead to higher and higherlevels of integration and miniaturisation,it will become increasinglydifficult to make the physical probing connections necessary for measurement and analysis.This will be especially important during system integration and later during product maintenance.It will undoubtedlylead to a significant increase in the use of standard logic-analyser businterfaces,such as VME,SCSl or the Aerospace I553 bus,to provide convenient probing connections to the system under analysis.
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